I am currently designing my custom Lighthouse tracker board based on the Lattice ICE40HX8K-CB132 FPGA and TS4231 Light to Digital Converter. The board is done using KiCad and supports up to 32 sensors. The board also has an RP2040 microcontroller used as a PC interface and an ICM-45686 IMU. The firmware for the RP2040 and gateware for the FPGA have been forked from Bitcraze, on the host PC you will need libsurvive. A possible future wireless extension is based on the nRF52833 used by SlimeVR Butterfly and Tundra trackers.
This talk introduces ElemRV, a lightweight open-source RISC-V microcontroller designed for accessibility and adaptability. We'll trace the project's origins and its first tape-outs using IHP's Open PDK, demonstrating how open-source silicon can move from concept to fabrication. The presentation covers ElemRV's architecture and key components, highlighting the design choices that shaped the microcontroller. We'll walk through the complete ASIC flow - from RTL source code to tape-out-ready GDSII files - demystifying the process of creating custom silicon with open-source tools. The session concludes with the roadmap for future tape-outs and planned enhancements, inviting community collaboration on this libre hardware project.
The f8 is an architecture for small embedded systems optimized for memory efficiency - regarding both code and data memory. We present the current state of the architecture (including the f8l variant for reduced core area), reference implementation, and the toolchain, which is based on the Small Device C Compiler (SDCC). https://github.com/f8-arch https://sdcc.sourceforge.net/
I have been working hands-on with FPGAs for open-source projects in distributed storage and networking. More recently, I have been interested to FPGA applications in finance and ultra–low-latency systems. Along the way, I found out that several open-source projects were immensely helpful, which made me realize that engineers and developers who want to get started could benefit from the same resources. This talk will cover the fundamentals of how, why, and where FPGAs are used in financial applications. Naturally, this talk will also highlight key open-source projects that can help the community build FPGA-based projects in this domain.
We will explore version 2.0 of the FABulous embedded FPGA (eFPGA) Framework and show how to design, implement, and simulate an embedded FPGA fabric. Starting from a high-level specification, we work towards a tiled and optimised, tapeout-ready physical layout (GDSII), in just a few steps.
FABulous is an easy-to-use, free and open-source eFPGA framework covering all aspects of what an FPGA ecosystem requires, from high-level design and layout to simulation and CAD tool integration. Version 2.0 introduces the ability to automatically generate a tiled and optimised physical layout, simplifying chip-level integration significantly.
The framework supports extensive customisation, including user-defined primitives, I/O cells, and integrating complex blocks such as CPU cores or ADCs. It has demonstrated superior area density in both standard-cell and custom-cell-based flows and has been validated across more than 15 manufactured chips, spanning 28 nm to 180 nm, including open (SKY130, IHP130, GF180) and industry (TSMC 180, 130, 28) PDKs. This demonstrates its practicality and adaptability across a wide range of design contexts.
GitHub: https://github.com/FPGA-Research/FABulous Docs: https://fabulous.readthedocs.io/en/latest/
The use of programmable logic devices, such as FPGAs, requires a range of software tools, from editors for HDL design to the place and route software that maps the design to the physical device and the software that handles the actual configuration process. These are often combined into a coherent IDE to improve efficiency and ease the learning process by offering smooth transitions between the different stages of development, from writing HDL via synthesis, simulation and implementation to the configuration of the device. In the world of FPGAs, these IDEs are mostly proprietary software, developed and owned by the few big FPGA vendors, that only support their own hardware. This means that once design flows are established around one vendor’s software suite, switching to a different vendor’s hardware becomes a tedious or even entirely unworkable task. For years now, pioneers in the open-source community have been steadily working to bridge the gap between commercial and open design tools, to the point that competitive solutions now exist for many aspects of FPGA design. With all the building blocks now available we in the FEntwumS project are now working to integrate a whole range of these tools into one coherent IDE that is as vendor-agnostic as possible and, most importantly, free and open-source. As a representative case study to validate and benchmark this platform, we integrate OpenEye, an open-source and fully FPGA-compatible neural network accelerator developed within the consortium. Its scalable architecture enables us to evaluate the robustness of the toolchain across different device classes and design configurations, testing synthesis behavior, implementation quality and runtime characteristics. By using OpenEye as a practical test vehicle, we ensure transparent evaluation, reproducibility and alignment with the open-source philosophy that underpins the entire project. In this talk, we will present our approach, our current progress, issues we have encountered and our future plans.