We will explore version 2.0 of the FABulous embedded FPGA (eFPGA) Framework and show how to design, implement, and simulate an embedded FPGA fabric. Starting from a high-level specification, we work towards a tiled and optimised, tapeout-ready physical layout (GDSII), in just a few steps.
FABulous is an easy-to-use, free and open-source eFPGA framework covering all aspects of what an FPGA ecosystem requires, from high-level design and layout to simulation and CAD tool integration. Version 2.0 introduces the ability to automatically generate a tiled and optimised physical layout, simplifying chip-level integration significantly.
The framework supports extensive customisation, including user-defined primitives, I/O cells, and integrating complex blocks such as CPU cores or ADCs. It has demonstrated superior area density in both standard-cell and custom-cell-based flows and has been validated across more than 15 manufactured chips, spanning 28 nm to 180 nm, including open (SKY130, IHP130, GF180) and industry (TSMC 180, 130, 28) PDKs. This demonstrates its practicality and adaptability across a wide range of design contexts.
GitHub: https://github.com/FPGA-Research/FABulous Docs: https://fabulous.readthedocs.io/en/latest/